1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to a method for fabricating of a semiconductor device with offset spacers.
2. Description of the Related Art
As MOSFET and CMOS device characteristic sizes are scaled below 0.1 microns, the process window for wet and dry etching processes for achieving desired critical dimensions are increasingly difficult. For example, in forming dielectric offset spacers, also referred to as sidewall spacers, it is particularly difficult to control the width of offset spacers and offset spacer liners with increasingly stringent process windows as device critical dimensions decrease. For example, the width of the offset spacer may be as small as 100 Angstroms (10 nanometers) or less in 65 nanometer critical dimension (gate length) CMOS devices.
A pair of offset spacers is formed adjacent to either side of the gate structure (gate dielectric and gate electrode) allowing the formation of source/drain regions thus enabling the offset spacers to act as an ion implant shield for forming a relatively higher doping level of n-type or p-type doping over source/drain (S/D) regions adjacent a lower doping level source drain extension (SDE) doped region formed adjacent the channel region underlying the gate dielectric.
As device critical dimensions (CD) shrink, achieving close dimensional tolerances of offset spacers is critical to achieving reliable electric performance and avoiding short channel effects (SCE). For example, source-drain extension (SDE) regions affect SCE according to both depth and width of the SDE doped region. The width of the offset spacers determines at least the width of the SDE regions. Offset spacer formation typically requires both deposition and etching processes, for example, to first deposit and subsequently remove portions of deposited dielectric layers. As device sizes shrink below about 0.13 microns both the deposition process and the etching process have extremely narrow process windows whereby dimensional variation undesirably alters CD and electrical performance of the CMOS device.
Conventional processes have typically included an oxide liner formed adjacent the gate electrode prior to formation of overlying nitride layers for forming the offset spacer. Generally in the spacer formation process, an oxide etching step is required to etch back a portion of the oxide liner overlying the gate electrode prior to carrying out subsequent processes such as silicide formation. Generally, the oxide liner layer is etched back by a wet etching process, which in conventional processes has caused undesirable undercut etching of the oxide liner in the oxide liner portion overlying the silicon substrate, for example in the SDE region. As a result, the critical widths of the offset spacer are compromised, leading to degradation of subsequent processing steps such as silicide formation over the source/drain region and leading to device performance degradation such as short channel effects (SCE) or gate oxide integrity (GOI).
Structures and fabrication methods have therefore been explored to solve the described problems. U.S. Pat. No. 6,448,167 B1 describes a composite insulator spacer on the sides of a MOSFET. Referring to FIG. 1a, an annealing procedure is used for both activation of the lightly doped source/drain region 4, and densification of the thin silicon oxide layer 5b. The etching rate of the densified silicon oxide layer 5b, in diluted hydrofluoric (HF) acid procedures is reduced, thus the underlying silicon oxide layer 5b of the composite insulator spacer reduces undercutting. The HF etching loss of the densified silicon oxide layer, however, is unavoidable. Device performance suffers from additional thermal budget, and fabrication costs are also increased.
U.S. Pat. No. 6,991,991 B2 discloses a method for preventing formation of a spacer undercut in the selective epitaxial growth (SEG) precleaning process. Referring to FIG. 1b, the method utilizes HF diluted by ethylene glycol (HFEG) solution to simultaneously etch a silicon oxide spacer 29A and a silicon nitride spacer; 29B of a spacer 29, for preventing spacer undercut. At the same time a native oxide layer upon a surface of a semiconductor substrate 20 is removed. Because nitride and oxide have an etching selectivity of about 2:1, thus reducing spacer undercutting. The HF etching loss of the silicon oxide spacer, however, is unavoidable.
Thus, a novel and reliable method of fabricating a semiconductor device with more robust sidewall spacer avoiding width altering effects of subsequent etching processes to thereby improve device performance is desirable.